Propagation delay modelling of MOS digital networks

An analytical model for the evaluation of propagation times in MOS digital networks is proposed. The model is an extension of the one proposed by J.P.C. Teixeira et al. (1987) and is based on the equivalent inverters concept. Rules for the characterization of equivalent inverters for CMOS complex gates and large combinational blocks, such as programmable logic arrays are derived and worst-case situations, in terms of time delays, are identified. A simple example is used to ascertain the accuracy and the usefulness of the proposed methodology. Extensions of the work towards automation are described