Title :
Active On-Die Suppression of Power Supply Noise
Author :
Keskin, Gökçe ; Li, Xin ; Pileggi, Larry
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA
Abstract :
An active on-chip circuit is demonstrated in 130nm CMOS for the suppression of on-chip power supply noise due to power distribution resonance. Testchip measurement results indicate up to 40% reduction in power supply noise during clock/power gating at a 2% power and 6% area overhead cost. Oscillation time is reduced by 50%. Simulation results show that comparable overshoot/undershoot and ringing control via on-chip decoupling would require significantly more area and power due to leakage, particularly at 90nm and below
Keywords :
CMOS integrated circuits; circuit oscillations; integrated circuit measurement; integrated circuit noise; integrated circuit testing; interference suppression; power supply circuits; 130 nm; CMOS process; active on-chip circuit; active on-die suppression; clock/power gating; on-chip decoupling; on-chip power supply noise; oscillation time; power distribution resonance; testchip measurement; Active noise reduction; Area measurement; Circuit noise; Circuit testing; Noise measurement; Power distribution; Power measurement; Power supplies; RLC circuits; Resonance; L.di/dt noise; damping and decoupling capacitor; power supply noise;
Conference_Titel :
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
1-4244-0075-9
Electronic_ISBN :
1-4244-0076-7
DOI :
10.1109/CICC.2006.321012
