The Multiplexed Structure of Multi-channel FIR Filter and its Resources Evaluation

When the multi-channel FIR filter is implemented in FPGA, the demands for resources are to be reduced. The paper optimized the structure of multi-channel FIR filter whose multi-channel input data are transported through time-multiplexed mechanism. In the optimized structure of multi-channel FIR filter which is implemented in FPGA the multi-channel input data share the same single-channel FIR filter. Compared to the typical structure of multi-channel FIR filter, the resource evaluation proves that when the optimized structure is formed by different kinds of single-channel FIR filter it achieves significant reduction in the demand of registers, and it is roughly the same or achieves significant reduction in the demands of multipliers and adders.