Title :
Separate dual-transistor registers: a circuit solution for on-line testing of transient error in UDMC-IC
Author :
Yi Shao ; Dey, Sujit
Author_Institution :
Electr. & Comput. Eng. Dept., California Univ., San Diego, CA, USA
Abstract :
This paper addresses the soft-error problem in UDSM circuits by presenting on-line fault-tolerant circuit design techniques. In our scheme, separate dual transistor (SDT) structure is introduced into the register design as a key component to increase the input-signal stability as well as the robustness of the circuit against the effects of ionizing particles. Our work not only demonstrates the feasibility of its physical implementation, but also shows the cost effectiveness. To compare with other fault-tolerant techniques, ISCAS89 circuits have been synthesized with the SDT standard cells to investigate its cost/timing overheads. Our benchmark comparison reveals its better applicability over two representative techniques (TMR and ECC) for the logic circuits in digital systems.
Keywords :
error detection; fault diagnosis; fault tolerance; integrated circuit design; integrated circuit testing; integrated logic circuits; logic testing; radiation hardening (electronics); transistor circuits; ISCAS89 circuits; SDT latch design; SDT standard cells; UDMC-IC; UDSM circuits; circuit hardening technique; circuit robustness; circuit solution; cost effectiveness; cost overheads; crosstalk; digital systems; electromagnetic noise; fault-tolerant techniques; input-signal stability; ionizing particles; logic circuits; on-line fault-tolerant circuit design techniques; on-line testing; physical implementation; register design; separate dual transistor structure; separate dual-transistor registers; sequential logic; signal integrity; soft-error problem; timing overheads; transient error; transmission line effects; ultra-deep-submicron circuits; voltage drop; Circuit stability; Circuit synthesis; Circuit testing; Costs; Digital systems; Fault tolerance; Logic circuits; Registers; Robust stability; Timing;
Conference_Titel :
On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE
Print_ISBN :
0-7695-1968-7
DOI :
10.1109/OLT.2003.1214359
