Title :
Designing FPGA based self-testing checkers for m-out-of-n codes
Author :
Matrosova, A. ; Ostrovsky, V. ; Levin, I. ; Nikitin, K.
Author_Institution :
Tomsk State Univ., Russia
Abstract :
The paper describes a specific method for designing self-checking checkers for m-out-of-n codes. The method is oriented to the field programmable gate arrays technology and is based on decomposing the sum-of-minterms corresponding to an m-out-of-n code. The self-testing property of the proposed checker is proven for a set of multiple stuck-at faults at input and output poles of a logic cell. An estimated complexity of obtained m-out-of-n checker demonstrates high efficiency of the proposed method.
Keywords :
automatic testing; codes; field programmable gate arrays; logic testing; FPGA based self-testing checkers; field programmable gate arrays; logic cell; m-out-of-n codes; multiple stuck-at faults; self-checking checkers; self-testing property; sum-of-minterms; Built-in self-test; Circuit faults; Circuit synthesis; Counting circuits; Design methodology; Distortion; Fault detection; Field programmable gate arrays; Programmable logic arrays; Switches;
Conference_Titel :
On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE
Print_ISBN :
0-7695-1968-7
DOI :
10.1109/OLT.2003.1214366
