Designing FPGA based self-testing checkers for m-out-of-n codes

The paper describes a specific method for designing self-checking checkers for m-out-of-n codes. The method is oriented to the field programmable gate arrays technology and is based on decomposing the sum-of-minterms corresponding to an m-out-of-n code. The self-testing property of the proposed checker is proven for a set of multiple stuck-at faults at input and output poles of a logic cell. An estimated complexity of obtained m-out-of-n checker demonstrates high efficiency of the proposed method.