Title :
Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation
Author :
Ogasahara, Yasuhiro ; Enami, Takashi ; Hashimoto, Masanori ; Sato, Takashi ; Onoye, Takao
Author_Institution :
Dept. Inf. Syst. Eng., Osaka Univ., Suita
Abstract :
Power integrity is an crucial design issue in nanometer technologies because of lowered supply voltage and current increase. This paper focuses on gate delay variation due to power/ground noise, and demonstrates measurement results in a 90nm technology. For full-chip simulation, a current model with capacitance and variable resistor is developed to accurately model current dependency on voltage drop. Measurement results are well correlated with simulation, and verify that gate delay depends on average voltage drop
Keywords :
circuit simulation; integrated circuit measurement; integrated circuit modelling; integrated circuit noise; power supply circuits; 90 nm; delay degradation; full-chip simulation; gate delay variation; power supply noise; variable resistor; voltage drop; Circuit noise; Circuit simulation; Degradation; Delay; Modeling; Noise measurement; Power measurement; Power supplies; Timing; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
1-4244-0075-9
Electronic_ISBN :
1-4244-0076-7
DOI :
10.1109/CICC.2006.320930
