The positive effect on IC yield of embedded fault tolerance for SEUs

Fault tolerant design is a technique emerging in Integrated Circuits (IC´s) to deal with the increasing error susceptibility (Soft Errors, or Single Event Upsets, SEU) caused by e.g. alpha particles. A side effect of these methods is that they also compensate for manufacturing defects (the Hard Errors). Currently, yield engineers focus on perfecting the manufacturing process and designers spend their effort in minimizing the area to increase the yield. In this paper, it is shown that increasing the IC area (by applying fault tolerant design techniques) leads under certain conditions to a better yield (more working dies from a wafer) and lower production cost. This is counter-intuitive for many design and yield engineers. To guide designers in deciding when the fault tolerant techniques are beneficial, break-even points between fault tolerant and regular design are presented as function of IC area, fault tolerant overhead and defect density.