DocumentCode
1682558
Title
Digital-PLL Assisted Frequency Estimation with Improved Error Variance
Author
Sithamparanathan, Kandeepan
fYear
2008
Firstpage
1
Lastpage
5
Abstract
In this paper we present a novel frequency estimation technique, assisted by an imperfect second order arctan based Digital Phase-Locked Loop (D-PLL), for complex single sinusoidal signals in additive white Gaussian noise. The imperfect loop contains the frequency information in its phase error process, at steady state, which is then used to estimate the frequency after the signal has been acquired by the D-PLL. For N samples, this particular estimator has a lower bound on the frequency error variance proportional to 1/N which is different to the well known Maximum Likelihood (ML) estimator that has a lower bound proportional to 1/N3 known as the Cramer-Rao bound (CRB). However, for given combinations of the loop parameters of the D-PLL, the error variance of the proposed estimator gives an improvement over the CRB for small values of N. We also present some detailed noise analysis on the proposed frequency estimator and derive a lower bound for the frequency error variance.
Keywords
AWGN; frequency estimation; maximum likelihood estimation; phase locked loops; Cramer-Rao bound; additive white Gaussian noise; digital-PLL; frequency error variance; frequency estimation; maximum likelihood estimator; phase locked loops; second order arctan; Additive white noise; Cramer-Rao bounds; Frequency estimation; Frequency locked loops; Maximum likelihood estimation; Phase estimation; Phase locked loops; Signal processing; State estimation; Steady-state;
fLanguage
English
Publisher
ieee
Conference_Titel
Global Telecommunications Conference, 2008. IEEE GLOBECOM 2008. IEEE
Conference_Location
New Orleans, LO
ISSN
1930-529X
Print_ISBN
978-1-4244-2324-8
Type
conf
DOI
10.1109/GLOCOM.2008.ECP.676
Filename
4698451
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