• DocumentCode
    1682631
  • Title

    Implementation of a dual segment architecture for a high pin count VLSI test system

  • Author

    Davis, Michael G.

  • Author_Institution
    LTX/Trillium, San Jose, CA, USA
  • fYear
    34608
  • Firstpage
    267
  • Lastpage
    272
  • Abstract
    This paper describes a dual segment VLSI test system architecture. It describes the design and cost goals that led us to this architecture. It also describes the direct and indirect benefits of this architecture
  • Keywords
    VLSI; automatic test equipment; automatic testing; computer architecture; integrated circuit testing; computer subsystem; cost; design; dual segment architecture; high pin count VLSI test system; pattern subsystem; Computer architecture; Costs; Hardware; Packaging; Pins; System testing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1994. Proceedings., International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-2103-0
  • Type

    conf

  • DOI
    10.1109/TEST.1994.527958
  • Filename
    527958
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1682631