Title :
Implementation of a dual segment architecture for a high pin count VLSI test system
Author :
Davis, Michael G.
Author_Institution :
LTX/Trillium, San Jose, CA, USA
Abstract :
This paper describes a dual segment VLSI test system architecture. It describes the design and cost goals that led us to this architecture. It also describes the direct and indirect benefits of this architecture
Keywords :
VLSI; automatic test equipment; automatic testing; computer architecture; integrated circuit testing; computer subsystem; cost; design; dual segment architecture; high pin count VLSI test system; pattern subsystem; Computer architecture; Costs; Hardware; Packaging; Pins; System testing; Very large scale integration;
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2103-0
DOI :
10.1109/TEST.1994.527958
