Spur-Free Fractional-N PLL Utilizing Precision Frequency and Phase Selection

An architecture for fractional-N frequency synthesis is presented. The proposed topology does not use the traditional method of obtaining the fractional division via an average of N and N+1 divided clock cycles. Instead, it uses the equally spaced phases provided from a ring oscillator that works as VCO to generate the fractional frequency. Therefore, the proposed architecture does not generate any spurs due to fractional frequency synthesis. As a result it provides better resolution for the fraction and avoids any compensation required for correction of the instantaneous jitter