Hazard-non-increasing gate-level optimization algorithms

Hazard-non-increasing optimization algorithms, optimizations on gate-level logic without introduction of any further static nor dynamic hazards, are presented. Proofs are given for general theoretical results on hazard-non-increasing transformations which serve as the basis for these algorithms. The algorithms substantially augment the set of proven hazard-non-increasing optimization techniques in the literature. These algorithms are useful for hazard-free implementations of asynchronous designs.<>