A comparative study of design for testability methods using high-level and gate-level descriptions

A comparative study of a gate-level test generator and a high-level test generator by benchmarking them on a common suite of circuits is presented. Based on the examination of the results DFT techniques that use high-level circuit information are proposed. The results obtained after partial scan selection by a high-level DFT tool are compared with results obtained by a gate-level partial scan tool. This detailed comparative study demonstrates that a DFT tool can make a more effective selection of partial scan flip-flops by exploiting the high-level circuit information, and by accurately predicting the hard-to-test areas of a circuit.<>