Title :
Behavioral synthesis for easy testability in data path scheduling
Author :
Lee, T.-C. ; Wolf, W.H. ; Jha, N.K.
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
Abstract :
A data path scheduling algorithm to improve testability without assuming any particular test strategy is presented. A scheduling heuristic for easy testability, based on previous work on data path allocation for testability, is introduced. A mobility path scheduling algorithm to implement this heuristic while also minimizing area is developed. Experimental results on benchmark and example circuits show high fault coverage, short test generation time, and little or no area overhead.<>
Keywords :
design for testability; logic testing; behavioural synthesis; benchmark; data path allocation; data path scheduling; design for testability; high fault coverage; mobility path scheduling algorithm; short test generation time; Design for testability; Logic circuit testing;
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1992.279303
