Three-phase chip planning-an improved top-down chip planning strategy

An improved top-down chip planning method that reduces the effects of differences of the estimated shapes in the floorplan and the final layouts are introduced. In a fully recursive approach, each cell is planned several times with different presumptions. Bottom-up adjustment steps use refined shape functions instead of rigid dimensions. Although such bottom-up adjustment steps were performed, the general direction is top-down. The convergence of the procedure can be ensured. The method is described in detail and some experimental results are provided. Several real large test designs (the largest example has nearly 300000 standard cells) have been performed with the PLAYOUT design system to compare the pure top-down approach with the new method.<>