Title :
Automatic synthesis of 3D asynchronous state machines
Author :
Yun, K.Y. ; Dill, D.L.
Author_Institution :
Comput. Syst. Lab., Stanford Univ., CA, USA
Abstract :
An automatic synthesis tool (3D) for designing asynchronous controllers from burst-mode specifications, a class of specifications allowing multiple input change fundamental mode operation, is described. An algorithm for constructing a three-dimensional next-state table, a heuristic for encoding states, and a procedure for generating necessary constraints for exact logic minimization are presented. The effectiveness of the 3D implementation and the synthesis procedure on numerous designs including a large realistic example (asynchronous data transfer protocol of the SCSI bus controller) is demonstrated. The latency (input to output delay) and the cycle time (time required for the circuit to stabilize after the excitation) for all benchmark designs using a 0.8- mu m CMOS standard cell library are estimated.<>
Keywords :
CMOS integrated circuits; asynchronous sequential logic; logic design; logic testing; minimisation of switching nets; 0.8 micron; 3D asynchronous state machines; CMOS standard cell library; SCSI bus controller; asynchronous controllers; asynchronous data transfer protocol; automatic synthesis; benchmark designs; burst-mode specifications; cycle time; encoding states; latency; logic minimization; synthesis procedure; three-dimensional next-state table; CMOS integrated circuits; Logic circuit testing; Logic design; Minimization methods;
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1992.279310
