• DocumentCode
    1683376
  • Title

    An efficient non-enumerative method to estimate path delay fault coverage

  • Author

    Pomeranz, I. ; Reddy, S.M.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
  • fYear
    1992
  • Firstpage
    560
  • Lastpage
    567
  • Abstract
    A method for estimating the coverage of path delay faults of a given test set, without enumerating paths, is proposed. The method is polynomial in the number of lines in the circuit, and thus allows circuits with large numbers of paths to be considered under the path delay fault model. Several levels of approximation, with increasing accuracy and increasing polynomial complexity, are proposed. Experimental results to show the effectiveness and accuracy of the estimate in evaluating the path delay fault coverage are presented. Combining this nonenumerative estimation method with a test generation method for path delay faults would yield a cost effective method to consider path delay faults in large circuits, which are beyond the capabilities of existing test generation and fault simulation procedures that are based on enumeration of paths.<>
  • Keywords
    computational complexity; fault location; logic testing; fault simulation; nonenumerative method; path delay fault coverage estimation; polynomial complexity; test generation method; Complexity theory; Fault location; Logic circuit testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
  • Conference_Location
    Santa Clara, CA, USA
  • Print_ISBN
    0-8186-3010-8
  • Type

    conf

  • DOI
    10.1109/ICCAD.1992.279312
  • Filename
    279312