Performance optimization of sequential circuits by eliminating retiming bottlenecks

A method to improve the effectiveness of retiming by transforming the sequential circuit is proposed. Bottlenecks which prevent retiming to achieve a desired clock period are identified. Conditions to eliminate the retiming bottlenecks are derived. These conditions are satisfied by a process of identifying subcircuits and satisfying a set of timing constraints on the subcircuits. The transformed circuit, which satisfies the timing constraints, can be retimed to achieve the desired clock period. If the original circuit has its initial state specified, the method always generates the final circuit with an equivalent initial state. Experimental results on a variety of sequential benchmark circuits demonstrate significant performance improvement.<>