Title :
A partitioning algorithm for system-level synthesis
Author :
Menez, G. ; Auguin, M. ; Boeri, F. ; Carriere, C.
Author_Institution :
Lab. d´Inf. Signaux et Syst., Nice Sophia-Antipolis Univ., France
Abstract :
The partitioning/scheduling/allocation algorithm developed for the CAPSYS method is presented. The aim of this project is to define a tool able to automatically design dedicated and embedded VLIW architectures for large and complex applications. It inherits a sizable knowledge-pool from the wider field of parallel processors, VLIW compiler design and high-level synthesis. Emphasis is placed on constraints of such a system synthesis approach and more especially on the particularity of the partitioning step. The proposed solution implements a software/hardware approach based on the list-scheduling heuristic.<>
Keywords :
circuit layout CAD; parallel architectures; program compilers; resource allocation; scheduling; CAPSYS method; VLIW compiler design; allocation algorithm; embedded VLIW architectures; high-level synthesis; list-scheduling heuristic; partitioning algorithm; system-level synthesis; Design automation; Parallel architectures; Program compilers; Resource management; Scheduling;
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1992.279323
