HERO: Hierarchical EMC-constrained routing

The authors point out that, in order to perform the design of printed circuit boards as time- and cost-efficiently as possible, electromagnetic compatability (EMC) phenomena have to be taken into account during layout synthesis. The EMC router HERO offers a robust framework for incorporating EMC constraints and cost criteria into routing. Using HERO, it will not be possible to obtain a completely failsafe layout, in general. However, experimental results for typical boards prove that a great number of EMC problems can be avoided during layout synthesis and that the effects of EMC phenomena can be reduced substantially. Detailed reports of EMC design rule violations provide effective input to the succeeding EMC verification phase. Violations of EMC design rules are mainly caused by an inappropriate placement. Therefore, it seems to be of great promise to combine hierarchical placement methods with this approach for hierarchical routing.<>