Title :
Zero skew clock routing in multiple-clock synchronous systems
Author :
Khan, W. ; Hossain, M. ; Sherwani, N.
Author_Institution :
Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
Abstract :
A clock routing algorithm for two-phase clock systems is presented. The algorithm, which minimizes both intraclock skew and interclock skew, has been implemented on SPARC 1+ in C and has been tested on several industrial benchmarks as well as on randomly generated examples. In particular, the result was tested for a 267 synchronous component circuit at clock rates of 100 MHz. It is significant that this is the first ever result which deals with multiple clock routing with zero skew.<>
Keywords :
circuit layout CAD; clocks; digital integrated circuits; network routing; synchronisation; 267 synchronous component circuit; SPARC 1+ in C; clock routing algorithm; interclock skew; intraclock skew; two-phase clock systems; zero skew clock routing; Clocks; Design automation; Digital integrated circuits; Routing; Synchronization;
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1992.279327
