Title :
A zero-skew clock routing scheme for VLSI circuits
Author :
Li, Y.-M. ; Jabri, M.A.
Author_Institution :
Dept. of Electr. Eng., Sydney Univ., NSW, Australia
Abstract :
A clock routing scheme that guarantees a zero-skew routing result is proposed. It is shown that the time complexity for the algorithm can be reduced to O(n/sup 2/ log n) by using the modified Voronoi diagram to structure the algorithm. L-shaped pairing and H-flipping operations are introduced to further reduce the clock wire length. Extensions are made to the algorithm for use in building-block layout and zero skew is also achieved. Significant reduction in total clock wire lengths is observed.<>
Keywords :
VLSI; circuit layout CAD; clocks; digital integrated circuits; H-flipping operations; L-shaped pairing; VLSI circuits; modified Voronoi diagram; total clock wire lengths; zero-skew clock routing scheme; Clocks; Design automation; Digital integrated circuits; Very-large-scale integration;
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1992.279328
