Title :
System-level routing of mixed-signal ASICs in WREN
Author :
Mitra, S. ; Nag, S.K. ; Rutenbar, Rob ; Carley, L.R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
Techniques for global and detailed routing of the macrocell-style analog core of a mixed-signal ASIC are discussed. A comparatively simple geometric model of the problem is combined with an aggressive simulated annealing formulation that selects paths while accommodating numerous signal-integrity constraints. Experimental results demonstrate that it is critical to attack such constraints both globally (system-level) and locally (channel-level) to meet designer-specified performance targets.<>
Keywords :
application specific integrated circuits; circuit layout CAD; simulated annealing; WREN; detailed routing; geometric model; global routing; macrocell-style analog core; mixed-signal ASICs; signal-integrity constraints; simulated annealing; system level routing; Application specific integrated circuits; Design automation; Simulated annealing;
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1992.279339
