Title :
A 100-Gb-Ethernet subsystem for next-generation metro-area network
Author :
Toyoda, Hidehiro ; Nishimura, Shinji ; Okuno, Michitaka ; Yamaoka, Ryouji ; Nishi, Hiroaki
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
An ultra high-speed Ethernet subsystem, which realizes 100-Gb/s throughput and transmission up to 40 km, is examined for next-generation metro-area networks. A parallel link of 12 10-Gb/s synchronized parallel optical lanes is proposed. The 10 optical lanes are used to transmit 10-bit parallel data. The one of redundant lanes transmits a forward error correction code ((132b, 140b) Hamming code) to achieve highly-reliable (BER < 10-12) data transmission, and the other lane transmits a parity data used for the fault-lane recovery. Here, a 64B/66B code-sequence-based de-skewing mechanism is proposed, and its effectiveness to realize low-latency compensation of the inter-lane skew (< 80 ns) is shown. We have implemented the 100-Gb-Ethernet interface architectures into FPGA circuits, and confirmed the performance of 100 Gb/s data communication with compact 385-kgates circuit size, which is practically small for implementation in a single LSI circuit.
Keywords :
Hamming codes; error correction codes; error statistics; field programmable gate arrays; forward error correction; local area networks; metropolitan area networks; telecommunication links; 100 Gbit/s; Ethernet interface architecture; Ethernet subsystem; FPGA circuit; Hamming code; code-sequence-based de-skewing mechanism; fault-lane recovery; forward error correction code; next-generation metro-area network; synchronized parallel optical lane; Bit error rate; Circuit faults; Data communication; Ethernet networks; Field programmable gate arrays; Forward error correction; High speed optical techniques; Large scale integration; Next generation networking; Throughput;
Conference_Titel :
Communications, 2005. ICC 2005. 2005 IEEE International Conference on
Print_ISBN :
0-7803-8938-7
DOI :
10.1109/ICC.2005.1494506
