Title :
Accurate layout area and delay modeling for system level design
Author :
Ramachandran, C. ; Kurdahi, F.J. ; Gajski, D.D. ; Wu, A.C.-H. ; Chaiyakul, V.
Author_Institution :
California Univ., Irvine, CA, USA
Abstract :
The problem of estimating design quality measures to accurately reflect design tradeoffs and efficiently explore the design space is discussed. Specifically, interest is centered on predicting the layout area and delay of a given structural RT level design. Clearly, current RT level cost measures are highly simplified and do not reflect the real physical design. In order to establish a more realistic assessment of layout effects, a layout model which accurately and efficiently accounts for the effects of wiring and floorplanning on the area and performance layout of RT level designs is proposed. Benchmarking has shown that this model is quite accurate.<>
Keywords :
circuit layout CAD; logic CAD; logic testing; RT level cost measures; benchmarking; delay modeling; design quality measures; design space; floorplanning; layout area; performance layout; real physical design; structural RT level design; system level design; wiring; Design automation; Logic circuit testing;
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1992.279347
