DocumentCode :
1684253
Title :
False loops through resource sharing (logic CAD)
Author :
Stok, L.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear :
1992
Firstpage :
345
Lastpage :
348
Abstract :
The effects of false loops caused by resource sharing are described. When a separate controller and data path are constructed, two types of false loops can be distinguished: the ones that go through the controller and the ones that loop around in the data path. A model to detect both types of loop during the resource sharing phase is described. Based on this model an algorithm which prevents false loops in the combinatorial network to be constructed, while maintaining as much freedom as possible for the resource sharing, is described. Experiments show that the loop-free data-paths do not need more functional units than the ones that contain false loops.<>
Keywords :
logic CAD; combinatorial network; controller; data path; false loops; logic CAD; loop-free data-paths; resource sharing; Design automation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
Type :
conf
DOI :
10.1109/ICCAD.1992.279349
Filename :
279349
Link To Document :
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