Title :
An approach to accelerate scan testing in IEEE 1149.1 architectures
Author_Institution :
Texas Instrum. Inc., USA
Abstract :
This paper describes an approach which can accelerate scan testing of combinational and sequential circuits within IEEE 1149.1 architectures. The approach can be used at both IC and system test levels, however most of the test time reduction benefits of this approach are seen at the system level
Keywords :
IEEE standards; automatic test equipment; boundary scan testing; combinational circuits; electronic equipment testing; fault diagnosis; integrated circuit testing; integrated logic circuits; logic testing; sequential circuits; IC testing; IEEE 1149.1 architectures; combinational circuits; delay testing; scan testing acceleration; sequential circuits; system test level; test time reduction; Circuit testing; Clocks; Combinational circuits; Instruments; Integrated circuit testing; Life estimation; Logic testing; Sequential analysis; Shift registers; System testing;
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2103-0
DOI :
10.1109/TEST.1994.527965
