E-PROOFS: A CMOS bridging fault simulator

Author

Greenstein, G.S. ; Patel, J.H.

Author_Institution

Sunrise Test Syst., Sunnyvale, CA, USA

fYear

1992

Firstpage

268

Lastpage

271

Abstract

The problem of bridging fault simulation under the conventional voltage testing environment is considered. A method to provide electrical-level simulation accuracy, without paying the associated performance penalties, is proposed. A three-level simulation model is used, balancing the tradeoffs among gate-level, switch-level, and electrical-level simulation. Large memory overheads are avoided by localizing the fault, and by performing electrical-level simulation only in the area around the fault. This approach is sufficiently flexible to model feedback faults, BiCMOS circuits, stuck-open faults, and any fault that can be described with a circuit netlist. Tests were run on several ISCAS combinational and sequential benchmark circuits, using realistic cells and transistor parameters; results show that accurate simulations can be performed in reasonable time.<>

Keywords

CMOS integrated circuits; circuit analysis computing; combinatorial circuits; fault location; integrated circuit testing; logic testing; sequential circuits; BiCMOS circuits; CMOS bridging fault simulator; E-PROOFS; ISCAS combinational circuits; electrical-level simulation accuracy; feedback faults; gate-level; large memory overheads; sequential benchmark circuits; stuck-open faults; switch-level; three-level simulation model; voltage testing environment; CMOS integrated circuits; Circuit simulation; Combinational logic circuits; Fault location; Integrated circuit testing; Logic circuit testing; Sequential logic circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on

Conference_Location

Santa Clara, CA, USA

Print_ISBN

0-8186-3010-8

Type

conf

DOI

10.1109/ICCAD.1992.279362

Filename

279362