ETA: electrical-level timing analysis

A timing analyzer which performs timing analysis considering electrical-level details such as input signal slope, gate input distinction, charge sharing, and interconnect, while also taking into account such high-level concerns as path sensitization, is described. To achieve the greatest efficiency, ETA operates in two phases: (1) logic and delay precharacterization, and (2) longest path analysis. During the precharacterization phase, each gate is analyzed to get its Boolean function and its load at the transistor level. During the longest path analysis phase, paths from each primary input are enumerated and examined separately. Each potentially longest path is tested for sensitizability at the gate level until a sensitizable longest path is found. The circuit examples given demonstrate the importance of an accurate delay calculation in correctly finding the longest statistically sensitizable path.<>