Optimal synthesis of multichip architectures

A global optimization approach to high level synthesis of VLSI multichip architectures is presented. Optimal application-specific architectures are synthesized to minimize latency given constraints on chip area, I/O pin count and interchip communication delays. A mathematical integer programming (IP) model for simultaneously partitioning, scheduling, and allocating hardware (functional units, I/O pins, and interchip buses) is formulated. By exploiting the problem structure (using polyhedral theory), the size of the search space is decreased and a new variable selection strategy is introduced based on the branch and bound algorithm. Multichip optimal architectures for several examples are synthesized in practical CPU times. Execution times are comparable to those for previous heuristic approaches. There are, however, significant improvements in optimal schedules and allocations of multichips.<>