Title :
A probabilistic timing approach to hot-carrier effect estimation
Author :
Li, P.-C. ; Stamoulis, G.I. ; Hajj, I.N.
Author_Institution :
Illinois Univ., Urbana, IL, USA
Abstract :
An approach for estimating hot-carrier induced degradation in MOS transistor circuits is presented. The approach uses probabilistic timing simulation techniques to estimate the cumulative effects of all possible inputs on hot-carrier effect (HCE) degradation in each transistor in the circuit in a single run rather than using exhaustive or Monte Carlo simulations. The approach has been implemented in a general-purpose simulator and tested on a number of typical examples and benchmarks.<>
Keywords :
MOS integrated circuits; Monte Carlo methods; circuit analysis computing; hot carriers; MOS transistor circuits; Monte Carlo simulations; benchmarks; general-purpose simulator; hot-carrier effect estimation; probabilistic timing approach; probabilistic timing simulation; Circuit simulation; Hot carriers; MOS integrated circuits; Monte Carlo methods;
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1992.279373
