Title :
An optimal chip compaction method based on shortest path algorithm with automatic jog insertion
Author :
Awashima, T. ; Yamamoto, W. ; Sato, M. ; Ohtsuki, T.
Author_Institution :
Dept. of Electron. & Commun. Eng., Waseda Univ., Tokyo, Japan
Abstract :
A one-dimensional compaction method for layout patterns including rectilinear macrocells on any number of layers is presented. The algorithm is based on the shortest path search on a constraint graph. It generates an optimal layout pattern in the smallest area by introducing effective jogs in O (N log N) time, where N is the number of line segments of the input pattern and inserted jogs. The jogs are inserted by means of an enhanced plane-sweep method developed in the field of computational geometry. Performance data of an experimental program show its efficiency.<>
Keywords :
circuit layout CAD; computational geometry; automatic jog insertion; computational geometry; constraint graph; enhanced plane-sweep method; input pattern; layout patterns; optimal chip compaction method; performance data; rectilinear macrocells; shortest path algorithm; Computational geometry; Design automation;
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1992.279382
