Identification of critical paths in circuits with level-sensitive latches

An approach to timing verification of circuits with level-sensitive latches which focuses on the critical paths that constrain the operating speed of these circuits is described. The timing model used has been referred to as the ´SMO model´ (Sakallah, Mudge and Olukotun, 1990). Three types of critical paths (long, short and loops) can arise in the SMO formulation; verifying their timing is sufficient to ensure correct operation. An algorithm for identifying these paths is presented, and its relationship to other approaches to solving the SMO model equations is discussed. Finally, results which demonstrate the algorithm on circuits from the ISCAS89 benchmark suite are presented.<>