Title :
Hybrid design for testability combining scan and clock line control and method for test generation
Author :
Baeg, Sanghyeon ; Rogers, William A.
Author_Institution :
Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
Abstract :
A hybrid DFT method is proposed to reduce the hardware penalty of traditional DFT methods and test generation time. It takes advantages of both traditional DFT methods like scan and DFT methods which control clocks for testability. The hardware scheme and test generation algorithm are presented. Test generation results for ISCAS ´89 circuits have been generated and showed an improvement in test generation time and fault coverage
Keywords :
automatic test equipment; boundary scan testing; clocks; design for testability; fault diagnosis; logic partitioning; logic testing; sequential circuits; DFT methods; ISCAS ´89 circuits; clock line control; design for testability; fault coverage; hardware penalty; hybrid design for testability; test generation; test generation time; Automatic test pattern generation; Circuit faults; Circuit testing; Clocks; Controllability; Costs; Design for testability; Hardware; Hybrid power systems; Sequential circuits;
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2103-0
DOI :
10.1109/TEST.1994.527968
