Title :
Rectification method for lookup-table type FPGA´s
Author :
Kukimoto, Y. ; Fujita, M.
Author_Institution :
Fujitsu Lab. Ltd., Kawasaki, Japan
Abstract :
A method to rectify lookup-table-type field-programmable gate array (FPGA) designs is presented. Instead of changing the netlist, only the functionality realized by lookup tables in a chip is modified and the netlist is retained so that there is no change in the delay of the chip. The problem is formalized using characteristic functions, and a redesign technique based on Boolean relations is presented.<>
Keywords :
Boolean functions; delays; logic CAD; logic arrays; table lookup; Boolean relations; FPGA; characteristic functions; delay; lookup-table-type field-programmable gate array; netlist; rectification method; redesign technique; Boolean functions; Delay effects; Design automation; Logic arrays; Table lookup;
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1992.279397
