DocumentCode :
1685336
Title :
An empirical evaluation of techniques for parallel discrete-event simulation of interconnnection networks
Author :
Miguel, Jose ; Arruabarrena, A. ; Beivide, Ramon ; Fortes, Jose A B
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fYear :
1996
Firstpage :
219
Lastpage :
226
Abstract :
Three parallel discrete-event simulators-synchronous, conservative and optimistic-implemented on an Intel Paragon multicomputer are comparatively evaluated. Parallelism is achieved by model decomposition, distributing the simulation among a set of collaborative logical processes. The three simulators differ in the way those processes synchronize to obey causal restrictions in the simulation of events. Message passing network models are used to study these simulation alternatives. A set of experiments are carried out to understand how model parameters influence simulator performance. Experimental evidence leads to the conclusion that the optimistic simulator is not a viable tool for the analysis of this kind of models. The opposite conclusion applies to the other two: if the workload assigned to each logical process is above a certain threshold then the synchronization overhead is comparatively low and the simulators perform and scale well up to a large number of processors. The performance threshold is influenced by some parameters of the simulated model (size of the network, load level and message length), as well as by the number of processors used by the simulators
Keywords :
discrete event simulation; message passing; multiprocessor interconnection networks; parallel programming; software performance evaluation; synchronisation; virtual machines; Intel Paragon multicomputer; causal restrictions; collaborative logical processes; conservative simulation; empirical evaluation; interconnnection networks; load level; message length; message-passing network models; model decomposition; model parameters; network size; optimistic simulation; parallel discrete-event simulation; performance threshold; process synchronization overhead; processor number; scalability; simulator performance; synchronous simulation; workload; Analytical models; Computational modeling; Computer simulation; Concurrent computing; Discrete event simulation; Intelligent networks; Message passing; Multiprocessor interconnection networks; Parallel processing; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Processing, 1996. PDP '96. Proceedings of the Fourth Euromicro Workshop on
Conference_Location :
Braga
Print_ISBN :
0-8186-7376-1
Type :
conf
DOI :
10.1109/EMPDP.1996.500590
Filename :
500590
Link To Document :
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