A tutorial on logic synthesis for lookup-table based FPGAs

Discusses combinational logic synthesis for FPGAs that use lookup tables (LUTs). Issues that differentiate LUT synthesis from conventional logic synthesis are emphasized. The ability of a K-input LUT to implement any Boolean function of K variables differentiates the synthesis of LUT circuits from that for conventional ASIC technologies. The major different occurs during the technology mapping phase of logic synthesis. For values of K greater than 3, the larger number of functions that can be implemented by a K-input LUT makes it impractical to use a conventional library-based technology mapping. However, the completeness of the set of functions that can be implemented by a LUT eliminates the need for a library of separate functions. In addition, this completeness can be leveraged to optimize the final circuit.<>