Title :
Aesthetic routing for transistor schematics
Author :
Lee, T.D. ; McNamee, L.P.
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Abstract :
A heuristic routing approach for generating transistor schematic diagrams is presented. The method consists of two steps: global routing and channel routing. The global routing step partitions and routes the interconnections, into three levels of abstraction with domain knowledge. It forms desirable intra-block routing styles and local connection patterns, and achieves a reduction of net bends and lengths. Channel routing minimizes net crossovers by applying decycling and ordering techniques achieving nonoverlapping routing with a small number of net crossovers.<>
Keywords :
VLSI; circuit diagrams; circuit layout CAD; network routing; transistor circuits; VLSI design; abstraction levels; aesthetic routing; channel routing; decycling; domain knowledge; global routing; heuristic routing approach; interconnections; intra-block routing styles; local connection patterns; net bends; net crossovers; net lengths; nonoverlapping routing; ordering techniques; transistor schematic diagrams; Design automation; Engineering drawings; Routing; Very-large-scale integration;
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1992.279400
