Title :
VLSI design parsing
Author_Institution :
Dept. of Comput. Sci., North Carolina Univ., Chapel Hill, NC, USA
Abstract :
The feasibility and efficiency of design parsing are discussed. Design parsing refers to the process of parsing a flat netlist or logic description into a behaviorally equivalent flow graph where the nodes correspond to higher-level primitives such as arithmetic functions and a prespecified set of functions. It is useful in verification, resynthesis and computer-aided design documentation. A spatial-entropy-based dynamic signature that helps determine the boundaries and types of function blocks is presented.<>
Keywords :
VLSI; circuit layout CAD; entropy; logic CAD; VLSI design parsing; arithmetic functions; behaviorally equivalent flow graph; boundary determination; computer-aided design documentation; flat netlist; function blocks; higher-level primitives; logic description; nodes; prespecified functions; resynthesis; spatial-entropy-based dynamic signature; type determination; verification; Design automation; Entropy; Very-large-scale integration;
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1992.279402
