VLSI design parsing

The feasibility and efficiency of design parsing are discussed. Design parsing refers to the process of parsing a flat netlist or logic description into a behaviorally equivalent flow graph where the nodes correspond to higher-level primitives such as arithmetic functions and a prespecified set of functions. It is useful in verification, resynthesis and computer-aided design documentation. A spatial-entropy-based dynamic signature that helps determine the boundaries and types of function blocks is presented.<>