Title :
New channel segmentation model and associated routing algorithm for high performance FPGAs
Author :
Burman, S. ; Kamalanathan, C. ; Sherwani, N.
Author_Institution :
Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
Abstract :
In the model considered, a channel is partitioned into several regions and each region consists of tracks of equal length segments, but segment length is varied uniformly across the regions. Each region is allocated a certain number of tracks. The segments are arranged in a staggered fashion. In order to make optimum use of the model, a routing algorithm is developed. The key feature of the routing algorithm is the assignment of the nets to the appropriate tracks by delay computation and delay matching techniques. Experimental results show that the model and the algorithm improve the longest net delay by as much as 75.16% and the average net delay by 48.28% as compared to the conventional uniformly segmented model.<>
Keywords :
circuit layout CAD; delays; logic arrays; network routing; average net delay; channel segmentation model; delay computation; delay matching techniques; equal length segments; field programmable gate arrays; high performance FPGAs; routing algorithm; segment length; track assignment; Delay effects; Design automation; Logic arrays; Routing;
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1992.279404
