Analysis and implementation of on-the-fly stopping criteria for layered QC LDPC decoders

This paper presents an analysis of existing stopping criteria for layered architecture used for quasi-cyclic (QC) LDPC decoders. Furthermore, it proposes a novel imprecise method for early termination in layered decoders. The analysis is performed under the same framework in order to provide a fair and accurate comparison between existing methods, and our new solution. The developed hardware modules have been designed independently from the decoder architecture, with the only constraint that the decoder scheduling is layered. Synthesis estimates for Xilinx Virtex-7 devices and the decoding performance analysis indicate that the new stopping criterion presents the best cost/performance trade-off for most of the considered LDPC codes.