Title :
In-system timing extraction and control through scan-based, test-access ports
Author_Institution :
Artificial Intelligence Lab., MIT, Cambridge, MA, USA
Abstract :
We present circuits and techniques which allow the extraction of fine-grained timing information using a simple, scan-based, test-access port such as the JTAG/IEEE 1149 standard. We go on to show how these techniques can be combined with other simple circuits for post-fabrication timing control. These techniques open up opportunities to perform timing oriented tests through TAP control. Further, they allow in-system timing adaptation which can be exploited to achieve high system performance
Keywords :
IEEE standards; boundary scan testing; integrated circuit testing; logic testing; timing; JTAG/IEEE 1149 standard; PLL; TAP control; calibration; delay adjustment; fine-grained timing; in-system timing adaptation; in-system timing extraction; post-fabrication timing control; sample register; scan-based test-access ports; timing oriented tests; Artificial intelligence; Circuit testing; Data mining; Delay; Fabrication; Laboratories; Latches; Phase locked loops; Registers; Timing;
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2103-0
DOI :
10.1109/TEST.1994.527969
