Design and implementation of the control structure of the PAPRICA-3 processor

The paper describes the pipeline architecture designed to control the execution of instructions on the linear array processor PAPRICA-9, which is being developed at the Politecnico di Torino. The main applications of the array processor lay in the area of image processing, image recognition, embedded systems for guidance assistance and the like. Exploitation of this architecture is currently investigated in the area of real time image processing, a very demanding task in terms of overall performance. Our design is aimed at improving the algorithmic efficiency by taking advantage of a multi path queue structure which allows different instructions to run simultaneously, and by optimizing particular patterns of instructions which often appear in envisaged application programs