Choosing the optimal HDL model of thermometer-to-binary encoder

Application of hardware description languages (e.g. Verilog, VHDL) to create design model and logic synthesis tools to generate its physical implementation is preferred design paradigm. In this paper it is examined how the modeling style used to implement the thermometer-to-binary encoder influence parameters of the synthesized circuit. It is demonstrated that badly chosen language statements and model structure may drastically deteriorate the delay, area and power consumption of the resulted circuit.