Data-folding in SRAM configurable FPGAs

FPGAs which are configured by static RAM can be rapidly changed from one logic configuration to another. This raises the possibility of configuring the logic to implement a function for a specific set of values, i.e. folding the inputs into the logic design. The paper discusses data folding with respect to Algotronix FPGAs, presenting a text searching circuit as an example. This folded circuit saves at least half the logic over a conventional circuit, and very much more if data folding is taken as far as possible. It also presents performance figures for the folded circuit, and discusses other applications, and suggests features which are desirable if data folding is to be practicable, most of which are possessed by the Algotronix CAL array