IF polyphase filter design and calibration with back-gate biasing in 28 nm FD-SOI technology

This paper presents a sixth-order IF polyphase band-pass filter design in 28 nm FD-SOI technology. This filter has been synthesized from a low-pass Butterworth filter prototype. The filter´s bandwidth is 1.2 MHz and its center frequency is 2 MHz. A calibration technique using back-gate biasing that is available in fully depleted SOI to minimize the mismatch impact, has been also described. The two filters have been designed using two different types of transistors (regular P/NMOS and flip-well P/NMOS). The power consumption is 1.4 mW. The simulation results of the designed filter have also been presented in this paper.