Title :
FPGA computing in a data parallel C
Author :
Gokhale, Maya ; Minnich, Ron
Author_Institution :
Supercomputing Res. Center, Bowie, MD, USA
Abstract :
The authors demonstrate a new technique for automatically synthesizing digital logic from a high level algorithmic description in a data parallel language. The methodology has been implemented using the Splash 2 reconfigurable logic arrays for programs written in Data-parallel Bit-serial C (dbC). The translator generates a VHDL description of a SIMD processor array with one or more processors per Xilinx 4010 FPGA. The instruction set of each processor is customized to the dbC program being processed. In addition to the usual arithmetic operations, nearest neighbor communication, host-to-processor communication, and global reductions are supported
Keywords :
C language; logic arrays; parallel languages; reconfigurable architectures; Data-parallel Bit-serial C; FPGA computing; SIMD processor array; Splash 2 reconfigurable logic arrays; VHDL description; Xilinx 4010 FPGA; arithmetic operations; data parallel C; data parallel language; dbC; global reductions; high level algorithmic description; host-to-processor communication; instruction set; nearest neighbor communication; Arithmetic; Automatic logic units; Concurrent computing; Field programmable gate arrays; Logic arrays; Logic programming; Parallel languages; Programmable logic arrays; Programming profession; Routing;
Conference_Titel :
FPGAs for Custom Computing Machines, 1993. Proceedings. IEEE Workshop on
Conference_Location :
Napa, CA
Print_ISBN :
0-8186-3890-7
DOI :
10.1109/FPGA.1993.279474
