Title :
A data-parallel programming model for reconfigurable architectures
Author :
Guccione, Steven A. ; Gonzalez, Mario J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
Recently, several machines have been built using field programmable gate array (FPGA) technology. These reconfigurable architectures have demonstrated very high performance for a variety of problems. The configuration of these machines typically rely on some form of hardware specification. The authors demonstrate that a more traditional software approach may be used. A vector based data-parallel model and its mapping to a reconfigurable architecture are introduced. Included in the model are parallel prefix or scan operators. The language supporting this model is a subset of the C programming language
Keywords :
logic arrays; parallel programming; reconfigurable architectures; C programming language; FPGA; data-parallel programming model; field programmable gate array; parallel prefix operator; parallel scan operator; reconfigurable architectures; vector based data-parallel model; Circuits; Computer architecture; Computer languages; Coprocessors; Field programmable gate arrays; Hardware; Microprocessors; Pipeline processing; Programming profession; Reconfigurable architectures;
Conference_Titel :
FPGAs for Custom Computing Machines, 1993. Proceedings. IEEE Workshop on
Conference_Location :
Napa, CA
Print_ISBN :
0-8186-3890-7
DOI :
10.1109/FPGA.1993.279476
