Title :
Spyder: a reconfigurable VLIW processor using FPGAs
Author :
Iseli, Christian ; Sanchez, Eduardo
Author_Institution :
Logic Syst. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland
Abstract :
A processor with multiple reconfigurable execution units has been designed and implemented. The reconfigurable execution units are implemented using reprogrammable field programmable gate array (FPGA) chips. The architecture and implementation of this processor are described in detail. An example shows that this reconfigurable processor is able to compute the new state of 100´000´000 cells of Conway´s game of life per second with a clock speed of 6.25 MHz
Keywords :
logic arrays; multiprocessor interconnection networks; reconfigurable architectures; 6.25 MHz; Spyder; game of life; multiple reconfigurable execution units; reconfigurable VLIW processor; reprogrammable field programmable gate array; Circuits; Clocks; Computer architecture; Field programmable gate arrays; Hardware; Laboratories; Logic design; Programmable logic arrays; Reconfigurable logic; VLIW;
Conference_Titel :
FPGAs for Custom Computing Machines, 1993. Proceedings. IEEE Workshop on
Conference_Location :
Napa, CA
Print_ISBN :
0-8186-3890-7
DOI :
10.1109/FPGA.1993.279483
