Modeling parasitic vertical PNP in HVCMOS

High voltage CMOS active devices inherently have a parasitic vertical bipolar transistor. The parasitic PNP structure can be activated during high-power switching operation causing a potential shift of the substrate. In this work a spice-modeling approach based on transistor layout is presented that is compatible with parasitic substrate noise propagation in Smart Power ICs. The results of the model are compared with TCAD simulations and show how the substrate network replaces the parasitic BJTs in HVCMOS compact models. Potential shift of the substrate is also analysed for different geometrical configurations showing the high flexibility of the proposed modeling approach.