Noise optimization of the time and energy measuring ASIC for silicon tracking system

This paper presents multi-objective optimization of a front-end electronics implemented in multichannel integrated circuit for silicon sensors readout in the Silicon Tracking System in the CBM experiment at the FAIR center. We present the optimization towards low-power (<; 8 mW/channel) and low-noise while keeping the channel pitch of 58 μm and minimum number of external components required for the circuit´s operation. Detailed study of the system noise (equivalent noise charge) with respect to a realistic model of the detector and interconnecting kapton microcable as well as realistic models of decoupling capacitors, wire-bonds and on-chip power distribution network are included.